1. Field of the Invention
The present invention relates to transmitting a logic signal having n bits. In particular, the invention relates to reducing power consumption by reducing a maximum value and/or an average value of the number of bits that are varied at the time of transmission, as compared to the corresponding values for the logic signal before transmission.
2. Description of the Related Art
In a logic LSI represented by a microprocessor, there exists a plurality of logic signal lines for the data transmission with other logic circuits via input/output pins. For instance, in the processor indicated in Power PC 601 RISC Microprocessor User's Manual, a signal line of 32 bit lines as a memory address line and a signal line of 64 bit lines as a data line are used.
Particularly, the data line is useful for transmitting a data value requested by a program to an outside circuit and the content of the transmitted data can be considered a random value. A logic gate having a large driving capability is used for driving a large capacitance outside of the logic LSI, as indicated in Sugano et al, "MOS LSI Design Introduction" (Industrial Publisher, page 199).
From the aspect of the power consumption reduction of the whole logic circuit, it is important to reduce the frequency of operation of the logic gate, because the logic gate charges and discharges a large amount of electric charges. A method for reducing a glitch caused by the combination logic and a method for changing the representation of data value from 2's complement representation to an absolute value representation are known as a technique for limiting the frequency signal variation transmitted to and from a logic circuit, as indicated in page 82, of "International Solid-State Circuits Conference" (ISSCC '94, agenda).